• DocumentCode
    648659
  • Title

    Graph based fault model definition for bus testing

  • Author

    Karimi, Ebrahim ; Haghbayan, M.H. ; Maleki, Ali ; Tabandeh, Mahmoud

  • Author_Institution
    Dept. of Electr. Eng., Sharif Univ. of Technol., Tehran, Iran
  • fYear
    2013
  • fDate
    7-9 Oct. 2013
  • Firstpage
    54
  • Lastpage
    55
  • Abstract
    In this paper we present a new fault model for testing standard On-Chip buses using a graph model. This method will be optimized for speed of testing. Using AMBA-AHB as the experimental result, the proposed fault model shows efficiency in comparison with corresponding stuck-at fault testing.
  • Keywords
    fault diagnosis; graph theory; integrated circuit modelling; integrated circuit reliability; integrated circuit testing; system buses; system-on-chip; AMBA-AHB; SoC; graph based fault model; on-chip buses testing standard; stuck-at fault testing; AMBA bus; Complemetntary graph; Fault model; Primary graph; SoC;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Very Large Scale Integration (VLSI-SoC), 2013 IFIP/IEEE 21st International Conference on
  • Conference_Location
    Istanbul
  • Type

    conf

  • DOI
    10.1109/VLSI-SoC.2013.6673246
  • Filename
    6673246
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=648659