DocumentCode
648666
Title
SyntHorus-2: Automatic prototyping from PSL
Author
Morin-Allory, Katell ; Javaheri, Fatemeh Negin ; Borrione, Dominique
Author_Institution
Tima Lab., UJF, Grenoble, France
fYear
2013
fDate
7-9 Oct. 2013
Firstpage
72
Lastpage
77
Abstract
We propose a linear complexity approach to achieve the automatic synthesis of designs from declarative temporal specifications. From each property, we produce a component that combines the features of signal monitors and generators: the reactant. This paper gives a formalization of a method to automatically decide which signals are observed and which are generated. The method is efficient, and synthesizes control circuits in a few seconds.
Keywords
electronic engineering computing; formal specification; logic design; signal generators; PSL; SyntHorus-2; automatic prototyping; declarative temporal specification; linear complexity approach; property specification language; signal generator; signal monitor; PSL; Synthorus; assertion-based design; automatic synthesis; correct by construction;
fLanguage
English
Publisher
ieee
Conference_Titel
Very Large Scale Integration (VLSI-SoC), 2013 IFIP/IEEE 21st International Conference on
Conference_Location
Istanbul
Type
conf
DOI
10.1109/VLSI-SoC.2013.6673253
Filename
6673253
Link To Document