An accurate power estimation model for low-power hierarchical-architecture SRAMs

Dedicated low-power SRAMs have become a crucial part of numerous applications, but various capacities, wordlengths and operational modes make it hard for designers to determine the best SRAM architecture. Additionally, many low-power techniques like hierarchical bitlines with local sense amplifiers and energy-efficient periphery circuits are typically utilized but not supported by previously proposed power models. To solve these problems, a fast and accurate power estimation model is proposed for aiding low-power SRAM designs. It operates as a parameter optimization tool and precisely fits the customized SRAM circuit and architecture. Specifically, the model is based on two major SRAM components: the address decoder and the memory array. It is verified that the estimation error of the model is less than 10% compared to results based on time-hungry extracted netlist simulations in a 40-nm CMOS technology.