Title :
IP-core protection for a non-volatile Self-reconfiguring SoC environment
Author :
Adi, Wibowo ; Zeitouni, Shaza ; Huang, Xumin ; Fyrbiak, Marc ; Kison, Christian ; Jeske, M. ; Alnahhas, Z.
Author_Institution :
Inst. of Comput. & Network Eng., Tech. Univ. Braunschweig, Braunschweig, Germany
Abstract :
Non-volatile Self-reconfiguring VLSI units with System-on-Chip (SoC) architecture are emerging as solutions for many modern applications. In this work, we propose a man-ufacturer and trusted authority-resistant, peer-to-peer protected Intellectual Property IP-exchange technique between SoC units. A Trusted Authority (TA) authenticates a post-manufacturing self-created random unknown Hardware-Software (HW-SW) secret digital function in each SoC unit. The unknown secret function, being implemented as a non-volatile structure, can serve as a permanent clone-resistant identity module for each unit. By using this clone-resistant identification infrastructure, a TA can help to establish a secured peer-to-peer IP-Core exchange protocol between any two such SoC units. Both trusted authority and SoC manufacturer have a temporary pure helping task without being able to clone units or disclose IP-cores. As IP-Cores (Bitstreams) reside in a non-volatile FPGA environment, the ciphering keys need a lifetime as short as the IP-core upload time. As a result, keys are not repeatable and can entirely be removed from the device after the IP-exchange session is completed. This makes the system more immune against Side Channel Attacks (SCA). The proposed system is low-cost, with scalable security and complexity. The system deploys long-term consistent pure digital architectures. It requires neither prior secret sharing between participants nor any extra transport of units other than a single initial physical authentication by a TA.
Keywords :
VLSI; cryptography; data privacy; field programmable gate arrays; logic circuits; microprocessor chips; system-on-chip; HW-SW; IP-core protection; IP-exchange technique; SCA; TA authentication; bitstreams; ciphering key; hardware-software secret digital function; long-term consistent pure digital architecture; nonvolatile FPGA environment; nonvolatile self-reconfiguring SoC environment; nonvolatile self-reconfiguring VLSI unit; peer-to-peer protected intellectual property-exchange technique; permanent clone-resistant identity module; side channel attack; single initial physical authentication; system-on-chip; trusted authority-resistant authentication; Adaptive and Evolvable Security; Clone-Resitant Units; Combined HW-SW Security Architectures; Digital PUF; IP Protection; Physical Security Anchor;
Conference_Titel :
Very Large Scale Integration (VLSI-SoC), 2013 IFIP/IEEE 21st International Conference on
Conference_Location :
Istanbul
DOI :
10.1109/VLSI-SoC.2013.6673284