Architectural exploration of a fine-grained 3D cache for high performance in a manycore context

New fine-grained 3D cache architectures have been recently proposed to embed more memory on-chip and thus reduce off-chip memory accesses. These 3D architectures provide a high access bandwidth thanks to wide vertical links. In this paper, we analyze the performances of such caches in a manycore context. We first propose to improve the microarchitecture of an existing 3D non uniform cache architecture. Then we evaluate the impact of the granularity (number of tiles) of this 3D cache on an existing multicore architecture executing high performance computing workloads. We show that the granularity of the 3D cache can affect the performances by a factor of 300%. We also evaluate the impact of the vertical links granularity (number of vertical 3D NoC links) on performances and show that a high number of these links is necessary to achieve the best performanes. Finally, we compare this fine-grained architecture to a memory using a Wide IO interface and show that the latter is less efficient in a manycore context.