Tagged probabilistic simulation based error probability estimation for better-than-worst case circuit design

Better than worst-case (BWC) design is an design emerging paradigm in which the conservative frequency guard-bands used in conventional designs are removed at the expense of introducing a a non-zero (but small) error probability. A fundamental challenge in the design of better-than-worst-case circuits is to devise scalable and accurate techniques for error-probability estimation - in this paper we present a new solution to address this challenge using the concept of tagged probabilistic simulations (TPS), which were first introduced in the context of dynamic power estimation. We show that TPS can, in comparison to the existing state-of-the-art, (a) provide consistent speed-up over error probability estimation using timing simulations; and (b) simultaneously provide estimates of both dynamic power dissipation and error probability. To illustrate the benefits of TPS based error probability estimation, we propose two power optimization techniques: a) a gate-level dual-VDD assignment tool b) a gate-sizing technique which optimize the cells used in a design for a certain error and power constraints.