A 65-nm CMOS area optimized de-synchronization flow for sub-VT designs

This paper proposes a process independent post layout de-synchronization flow implemented in tool command language working on designs operating in the sub-V_T regime. The overhead due to the self-timed operation is combated by introducing full-custom delay elements and latches for a standard 65-nm CMOS process. The flow offers the possibility to adjust granularity based on user requirements. Case studies with different reference designs manifested an average reduction of area and power overhead from 105% to 9% and 174% to 58% in comparison to a full standard cell de-synchronization approach.