Making digital systems design more convenient to students by means of visualization

Thanks to the ever-growing complexity of contemporary digital systems the HDLs (Hardware Description Languages) and EDA (Electronic Design Automation) tools have became an inevitable part of the digital design process. To make the HDL model´s complexity better manageable graphical representation of its structure is often required. Also to browse the models´ extensive simulation results the proper representation is needed especially for students and beginners. In this contribution the visualization methods for digital systems models´ structure and simulation results have been proposed. The methods covering the most widely used HDLs - namely Verilog, VHDL, and SystemC, have been integrated into the visualization framework allowing to visualize and browse the model´s structure on all hierarchical levels, enabling also to visualize simulation results directly in the displayed structure. Thanks to the adoption of unified formats to represent models´ structure and simulation results the framework can be extended to support other HDLs. However, the simulation results can also be displayed in the traditional waveform style to improve the verification capability.