Designing a low-power wireless sensor node rASIP architecture

Wireless sensor nodes are an emerging key technology of the 21^st century. Increasing demands towards node capabilities such as video streaming and secure transmission are a great challenge with respect to providing required high performance while maintaining low power consumption. Within the SMART project funded by ARTEMIS-JU, a novel architecture for such high-performance sensor nodes was developed. Key feature of this node is a dedicated processing unit, called rASIP, providing required flexibility and high performance at low energy requirements. In this paper we introduce the rASIP architecture, outline its requirements-driven development process, and present the resulting architecture. Using different fabrication processes enables further fine-tuning towards specific node requirements, which we illustrate by performance numbers for standard ASIC processes and a dedicated low-leakage process.