DocumentCode :
649037
Title :
Design and implementation of a high throughput soft output MIMO detector
Author :
Yin-Tsung Hwang ; Yi-Yo Chen
Author_Institution :
Nat. Chung Hsing Univ., Taichung, Taiwan
fYear :
2013
fDate :
16-18 Oct. 2013
Firstpage :
124
Lastpage :
129
Abstract :
In this paper, a new soft output MIMO decoder based on the k-best search scheme and additional partial Euclidian distance (PED) update schemes is developed. The k-best framework facilitates a constant throughput implementation and the PED update schemes help achieve a more accurate log-likelihood ratio (LLR) calculation. A LLR clamping technique is further adopted to enhance the BER performance when combining with the LDPC coding. Simulation results indicate the effectiveness of the proposed PED update schemes against previous works. Efficient architecture design is next developed capable of accomplishing one 4×4 MIMO signal vector detection every 4 clock cycles. In FPGA implementation, the maximum working frequency can be up to 121.3MHz and suggests a 720Mbps data rate for a 4×4 MIMO system using 64QAM modulation.
Keywords :
MIMO communication; field programmable gate arrays; integrated circuit design; parity check codes; search problems; signal detection; 64QAM modulation; BER performance; FPGA implementation; LDPC coding; LLR clamping technique; MIMO signal vector detection; architecture design; constant throughput implementation; high throughput soft output MIMO detector; k-best framework; k-best search scheme; log-likelihood ratio calculation; partial Euclidian distance update schemes; soft output MIMO decoder; FPGA; MIMO signal detector; k-best search; soft output;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Processing Systems (SiPS), 2013 IEEE Workshop on
Conference_Location :
Taipei City
ISSN :
2162-3562
Type :
conf
DOI :
10.1109/SiPS.2013.6674492
Filename :
6674492
Link To Document :
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