A conflict-free memory mapping approach to design parallel hardware interleaver architectures with optimized network and controller

Recent communication standards and storage systems (e.g. wireless access, digital video broadcasting or magnetic storage in hard disk drives) uses error correcting codes such as LDPC (Low Density Parity Check) or Turbo-codes to reliably transfer data between source and destination. For high data rate applications, Turbo and LDPC codes are decoded on parallel architectures. However, parallel architectures suffer from memory access conflicts and efficient memory mapping algorithms are required to design parallel interleaver architectures which are one of the most critical parts of parallel decoders. In this paper, we present a method that finds a conflict-free memory mapping for any interleaving law and associated parallelism constraint. The proposed approach always complies with the interconnection network topology the designer wants to infer. Moreover, contrary to traditional methods, the resulting architecture is optimized by reducing the cost of network and controller (network and memory controller) architectures. Our approach is compared with state of the art techniques and its interest is shown through the design of parallel interleavers used in different industrial applications such as High Speed Downlink Packet Access (HSDPA), Multi Band-Orthogonal Frequency-Division Multiplexing Ultra-WideBand (MB-OFDM UWB) and a WiMAX application.