Low power Null Convention Logic circuit design based on DCVSL

Null convention logic units are the most important logic units in asynchronous circuits. This paper propose a new design of Null Convention Logic(NCL) design method based on the differential cascode voltage-switch logic (DCVSL). Comparisons are analyzed on delay and power consumption between the conventional NCL circuits design methods and our proposed NCL circuit deisgn method. After each single NCL gate designs have been simulated and compared, the overall performance of the proposed NCL circuits design technique is compared with the previous designs with a test case of the 4×4 multiplier implementation in 110nm CMOS technology node. The comparison of NCL basic gates shows that the proposed design approach achieves more than 20% power savings and more than 30% delay improvement as well as transistor count reduction. These performance and power saving are also verified in 4×4 multiplier design case.