• DocumentCode
    649118
  • Title

    Variability robustness enhancement for 7nm FinFET 3T1D-DRAM cells

  • Author

    Amat, Esteve ; Almudever, C.G. ; Aymerich, N. ; Rubio, Albert ; Canal, Ramon

  • Author_Institution
    Electron. Eng. Dept., Univ. Politec. de Catalunya, Barcelona, Spain
  • fYear
    2013
  • fDate
    4-7 Aug. 2013
  • Firstpage
    81
  • Lastpage
    84
  • Abstract
    3T1D-DRAM cells will still be operative with 7nm FinFETs but their performance is significantly degraded when factoring in variability. In order to improve the cell robustness against device process variation and high environment temperatures, we propose a Dual-VT strategy. Our results show a larger retention time, significant cell spread reduction and reliable behavior up to 100°C.
  • Keywords
    DRAM chips; MOSFET; FinFET 3T1D-DRAM cells; cell robustness; cell spread reduction; device process variation; dual-VT strategy; environment temperatures; retention time; size 7 nm; variability robustness enhancement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (MWSCAS), 2013 IEEE 56th International Midwest Symposium on
  • Conference_Location
    Columbus, OH
  • ISSN
    1548-3746
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2013.6674590
  • Filename
    6674590
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=649118