Design strategy for enhanced output impedance current-steering DAC in sigma-delta converters

This paper analyses the design trade-off of a high-output impedance current mirror structure used as a current-steering DAC in a sigma-delta modulation DAC with dynamic element matching. The aim is to provide a design strategy with transistor sizing guidelines leading to the achievement of high static linearity and high accuracy given specific accuracy, load resistance, and voltage swing requirement. Challenging factors limiting the circuit static linearity are described and shown. A test chip implemented in 180nm CMOS process has been designed and fabricated, with simulated results showing static linearity of a 16-bit DAC has been achieved.