A configurable fault-tolerant glitch-free clock switching circuit

This paper has analyzed the conventional glitch-free clock multiplexers. An improved glitch-free clock switching circuit is proposed, which introduces fault-tolerant function that is able to switch away from a failed clock, and adds configurable bit that controls the switching clock edge. It is quite suitable used as a global clock multiplexer in FPGA. This switching circuit achieves three basic functions: clock select, clock enable, and clock disable. As the configurable low-level triggered latch is proposed, switching time is reduced by 1/3 compared to the double D flip-flops type clock multiplexer. This proposed switching circuit operates at 100 MHz with 17uW power consumption using TSMC 0.13um CMOS process parameters with a supply voltage of 1.5V.