On the settling of nondelaying cascaded switched-capacitor integrators

This paper focuses on the design of two nondelaying cascaded SC integrators. Given the importance of good settling in SC filters, a design method is presented which optimizes the power consumption for a given settling accuracy. Another issue is also addressed concerning a possible excitation case that might lead to settling “hesitation” in two nondelaying cascaded SC integrators which affects settling accuracy. Circuit simulations confirm the analytical methods and simulations. The proposed analytical equations can be easily embedded into behavioral models used for large system´s simulations in early design stages.