Title :
Path delay testing in resilient system
Author :
Qiang Han ; Jianghao Guo ; Wen-Ben Jone ; Qiang Xu
Author_Institution :
Sch. of Electron. & Comput. Syst., Univ. of Cincinnati, Cincinnati, OH, USA
Abstract :
Resilient systems are designed to eliminate the voltage/frequency margin for further power reduction/performance improvement. With the occurrence of error detection sequential (EDS) circuits and error-path circuits, resilient systems bring in new challenges for the path delay testing. In this paper, three scan EDS designs are analyzed and compared. Then a novel OR-tree delay testing method is proposed and experimental comparison is made showing our method´s higher efficiency than a baseline method.
Keywords :
delays; error detection; logic design; logic gates; logic testing; sequential circuits; EDS circuit; OR-tree delay testing method; error detection sequential circuits; error-path circuits; path delay testing; power reduction; resilient system; scan EDS designs; voltage-frequency margin;
Conference_Titel :
Circuits and Systems (MWSCAS), 2013 IEEE 56th International Midwest Symposium on
Conference_Location :
Columbus, OH
DOI :
10.1109/MWSCAS.2013.6674731
