A variable-bandwidth, power-scalable optical receiver front-end in 65 nm

This work presents the design and simulated performance of a variable bandwidth, power-scalable optical receiver front-end in 65 nm CMOS technology. The proposed receiver front-end includes a transimpedance amplifier (TIA) and 3-stage post-amplifier with an offset compensation loop. The proposed TIA is based on the shunt feedback topology while the post amplifier and the offset-compensation loop use the Cherry-Hooper inverter-based topology. In order to make the receiver power and bandwidth scalable a binary-weighted current-controlled MOSFET array and a tunable resistance bank are also proposed. The receiver front-end can vary the supported data rate from 1.25 Gb/s to 20 Gb/s with proportional power dissipation with a constant gain of ~75 dBΩ. The overall power dissipation varies from 0.32 mW to 13.5 mW as the data rate scales maintaining an energy per bit lower than 700 fJ at all data rates. The variable 3 dB bandwidth is from 0.85 GHz to 13.5 GHz with input referred noise density from 8.46 pA/√(Hz) to 18 pA/√(Hz). With the offset-compensation loop active, the dc operating point of the receiver front-end requires 140 ps to settle when the data rate is reconfigured from 1.25 Gb/s to 20 Gb/s.