Tradeoffs between settling time and jitter in phase locked loops

In most phase locked loops, an obvious trade-off exists between settling time, output jitter and power consumption. However, dependence of jitter on settling time is commonly ignored while evaluating PLL designs. In this paper, the tradeoffs between settling time and jitter is analyzed for different types of All-Digital PLLs (ADPLLs). Based on these analytical results, a Figure of Merit (FoM) for evaluating PLLs, which takes settling time into consideration, is suggested. Survey carried out over state-of-the-art PLLs indicates that the proposed FoM provides a much better trend compared to previously used FoM that does not take the settling time into account. Finally, a 2.4-GHz Direct-Digital Synthesis based AD-PLL model, which combines phase detection switching, adaptive gain and FSM based mechanism, is explored to gain simultaneous optimization of PLL performance parameters.