High level circuit synthesis with system level Statistical Static Timing Analysis under process variation

Process variations are of great concern in deep submicron technology. Early prediction of their effects on the circuit performance and parametric yield is extremely useful. Due to the increase of the design complexity in today´s SoC chips, a demand for high level design has increased. Therefore, in this paper, we propose the timing analysis model so that the impact of process variations is taken into account during high level synthesis. In experiments, the proposed method have showed very minor variances of 1.67% at the 85% timing yield constraint (TYC) and of 0.26% at the 99% (3σ) TYC, as opposed to Monte-Carlo simulation. In our approach, we consider the spatial and path reconvergence correlations between path delays, set-up and hold time constraints, as well as skew due to process variations.