A time-to-digital converter (TDC) with a 13-bit cyclic time domain successive approximation interpolator with sub-ps-level resolution using current DAC and differential switch

A new architecture of the time-to-digital converter (TDC) aims at adjustable sub-ps-level resolution with high linearity in ms-level dynamic range. To achieve sub-ps-level resolution with cyclic time domain successive approximation (CTDSA) within a clock cycle, the propagation delay difference is implemented by digitally controlling both the unit load capacitors and the discharge current of the load capacitance. The proposed CTDSA achieves 610 fs resolution and ~5 ns dynamic range. The total simulated power consumption is 63.3 mW with 3 V supply. The design was simulated using a 0.35 μm CMOS process.