An 8-bit 500kS/s semi-digital cyclic ADC with time-mode residue voltage generation

This work presents a semi-digital cyclic ADC with time-mode residue voltage generation. In the proposed scheme, the conventional switched-capacitor MDAC is replaced with a time-mode circuit which generates the residue voltage by controlling the charge and discharge interval of a capacitor. As a result, a semi-digital cyclic ADC can be realized using simple circuit components including capacitors, comparators, DC current source, and digital logics. Without the amplifier, the analog blocks can operate under a lower supply voltage that leads to reduced power consumption. Furthermore, a compact ADC can be realized by using small sized capacitors. An 8-bit, 500kS/s cyclic ADC is realized using CMOS 0.35μm technology, where the power consumption is 36.7μW.