DocumentCode :
649311
Title :
Enabling high-speed, high-resolution ADCs using signal conditioning algorithms
Author :
Ghosh, A. ; Pamarti, Sudhakar
Author_Institution :
Dept. of Electr. Eng., Univ. of California, Los Angeles, Los Angeles, CA, USA
fYear :
2013
fDate :
4-7 Aug. 2013
Firstpage :
856
Lastpage :
859
Abstract :
Time-interleaving several identical A/D converters enhances the overall conversion speed in a power-economical way. However, mismatches between individual channels in such schemes degrade the overall dynamic range of the converter. Several algorithms to mitigate such effects are discussed with special emphasis on an adaptive signal-conditioning algorithm. The algorithm is further extended towards a hardware-friendly implementation using interpolation filters. Behavioral simulations corroborating the same are presented.
Keywords :
analogue-digital conversion; filters; interpolation; signal conditioning circuits; A/D converter; ADC; adaptive signal-conditioning algorithm; hardware-friendly implementation; interpolation filter; power-economical way; time-interleaving converter;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (MWSCAS), 2013 IEEE 56th International Midwest Symposium on
Conference_Location :
Columbus, OH
ISSN :
1548-3746
Type :
conf
DOI :
10.1109/MWSCAS.2013.6674784
Filename :
6674784
Link To Document :
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