Systematic synthesis of cascaded continuous-time ΔΣ ADCs for wideband data conversion

Continuous-time delta sigma (CT-ΔΣ ) ADCs are gaining wider adoption in data conversion systems primarily aided by their robustness to mismatch in nano-scale CMOS technologies and inherent anti-alias filtering. In past, several techniques have been employed to achieve wider conversion bandwidths by either scaling the designs to a lower technology node or by adopting architectures with lower oversampling ratios (OSR). Cascaded, or MASH, CT-ΔΣ ADCs have been explored to achieve conversion bandwidths by cascading lower order ΔΣ loops followed by a digital coarse quantization noise canceling filter (NCF). Another technique which has recently been explored is to increase the quantizer sampling rate, in a given technology node, by absorbing excess loop-delay (ELD) greater than one clock cycle (T_s) in the loop. However, these techniques individually cannot sufficiently meet the ever increasing bandwidth demand for the broadband wireless applications. Further, the ELD > T_s designs require an extra modulator order to achieve the same noise-shaping performance as the low-speed ELD <; 0.5 T_s prototype, necessitating high-order CT-ΔΣ loops. As a step towards combing the two techniques, we propose a systematic design method to synthesize 3-2 MASH CT-ΔΣ modulators to achieve higher conversion bandwidths, BW ≥ 40MHz in a 130-nm CMOS technology.