A 6-bit 1.5GS/s pipelined binary search ADC with simplified clocking scheme

A new high speed, and low power ADC architecture and its circuit implementation is introduced in this paper. Proposed ADC takes the advantage of low power characteristic of SAR ADCs and combines it with high speed operation of pipeline ADCs to realize a high throughput energy efficient ADC. By unrolling the feedback loop of SAR ADC and delaying the analog signal the binary search algorithm is implemented in pipeline mode. The analog delay is implemented using time interleaved sampling scheme. Since no residue amplifier is required in the proposed ADC, significant high speed yet low power operation can be achieved simultaneously. A 6-bit, 1.5-GS/s ADC is designed based on this concept in a 65nm CMOS process. Simulations confirm that the proposed ADC achieves an SNDR of 35.63dB, ENOB of 5.63, and FoM of 78fJ/conv-step for a Nyquist rate input frequency while consuming 5.8mW from a single 1.2V power supply.