The SyReC hardware description language: Enabling scalable synthesis of reversible circuits

While reversible logic increasingly finds useful application as an emerging technology for various areas, the design of corresponding circuit structures still is in its infancy. Most of the existing approaches for synthesis or optimization are applicable for relatively small functions only. Hardware description languages enable to overcome this limitation. Combined with hierarchical synthesis schemes, they allow for the specification and realization of complex logic as a reversible circuit. On the other side, the resulting synthesis schemes lead to further challenges, e.g. a significant increase in the number of additional circuit signals. In this paper, we provide an overview on the design of reversible circuits through the hardware description language SyReC. This includes a summary of the recently made accomplishments as well as a discussion of challenges still to be addressed.