DocumentCode :
649380
Title :
High-parallel performance-aware LDPC decoder IP core design for WiMAX
Author :
Xiongxin Zhao ; Zhixiang Chen ; Xiao Peng ; Dajiang Zhou ; Goto, Satoshi
Author_Institution :
Grad. Sch. of IPS, Waseda Univ., Kitakyushu, Japan
fYear :
2013
fDate :
4-7 Aug. 2013
Firstpage :
1136
Lastpage :
1139
Abstract :
In this paper, we propose a synthesizable LDPC decoder IP core for the WiMAX system with high parallelism and enhanced error-correcting performance. The proposed fully-parallel layered decoder architecture can fully support multi-mode decoding specified in WiMAX with 12~24 clock cycles for processing one iteration. By applying the 3-state processing schedule, it achieves twice parallelism with minor circuit area increase compared to state-of-the-art work, thus results in 46.8% improvement in power efficiency.
Keywords :
IP networks; WiMax; error correction codes; iterative decoding; parity check codes; 3-state processing schedule; WiMAX; error correcting performance; high-parallel performance-aware LDPC decoder IP core design; iterative decoding; multimode decoding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (MWSCAS), 2013 IEEE 56th International Midwest Symposium on
Conference_Location :
Columbus, OH
ISSN :
1548-3746
Type :
conf
DOI :
10.1109/MWSCAS.2013.6674853
Filename :
6674853
Link To Document :
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