Power efficient SAR ADC with optimized settling technique

This paper presents a 12-bit 50-MS/s successive-approximation (SAR) analog-to digital (ADC) with high power efficiency. By splitting MSB capacitors an efficient step switching scheme is proposed to reduce average switching energy of the capacitive DAC by 93.75% as compared to conventional method. The settling time is partially optimized in half of the conversion steps. Prototype is designed in a 65-nm CMOS technology and the power consumption is 2.0mW under a 1.2-V power supply.