DocumentCode
649385
Title
Power efficient SAR ADC with optimized settling technique
Author
Weiru Gu ; Hao Zhou ; Tao Lin ; Zhenyu Wang ; Fan Ye ; Junyan Ren
Author_Institution
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
fYear
2013
fDate
4-7 Aug. 2013
Firstpage
1156
Lastpage
1159
Abstract
This paper presents a 12-bit 50-MS/s successive-approximation (SAR) analog-to digital (ADC) with high power efficiency. By splitting MSB capacitors an efficient step switching scheme is proposed to reduce average switching energy of the capacitive DAC by 93.75% as compared to conventional method. The settling time is partially optimized in half of the conversion steps. Prototype is designed in a 65-nm CMOS technology and the power consumption is 2.0mW under a 1.2-V power supply.
Keywords
CMOS integrated circuits; analogue-digital conversion; capacitors; digital-analogue conversion; low-power electronics; CMOS technology; MSB capacitors; analog-to digital; capacitive DAC; optimized settling; power 2.0 mW; power consumption; power efficient SAR ADC; size 65 nm; step switching; successive-approximation; voltage 1.2 V; word length 12 bit;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (MWSCAS), 2013 IEEE 56th International Midwest Symposium on
Conference_Location
Columbus, OH
ISSN
1548-3746
Type
conf
DOI
10.1109/MWSCAS.2013.6674858
Filename
6674858
Link To Document