Title :
Fused floating-point magnitude unit
Author :
Jae Hong Min ; Swartzlander, Earl E.
Author_Institution :
Electr. & Comput. Eng. Dept., Univ. of Texas at Austin, Austin, TX, USA
Abstract :
A new fused floating-point magnitude unit to compute the square-root of the sum of two squares is proposed. Conventionally, the magnitude computation is executed by discrete serial or parallel floating-point units with conventional floating-point multiplication, squares, addition, and square-root units. The proposed fused floating-point magnitude design has an enhanced exponent unit because the exponent processes of the sum-of-squares and square-root can be merged. Moreover, normalization to make the exponent an even number is not necessary for the fused magnitude unit. Normalization and rounding processing between the squares, addition and square-root computations are eliminated. This paper compares the fused magnitude unit with the conventional discrete floating-point magnitude units. Compared with the discrete parallel magnitude unit with conventional floating-point squarers, an adder, and a square-root unit, the fused floating-point magnitude unit has 24% less area, 24% less latency, and 27% less power consumption (26% less in the pipeline model).
Keywords :
adders; floating point arithmetic; logic design; adder; addition; discrete floating-point magnitude units; discrete parallel magnitude unit; discrete serial floating-point units; exponent processes; exponent unit; floating-point magnitude design; floating-point multiplication; floating-point squarers; fused floating-point magnitude unit; magnitude computation; parallel floating-point units; square-root units; sum-of-squares; floating-point magnitude unit; fused floating-point arithmetic unit; low-power floating-point arithmetic unit;
Conference_Titel :
Circuits and Systems (MWSCAS), 2013 IEEE 56th International Midwest Symposium on
Conference_Location :
Columbus, OH
DOI :
10.1109/MWSCAS.2013.6674914