On a parallel decimal multiplier based on hybrid 8421–5421 BCD recoding

Parallel decimal multiplications can be broadly divided into two major steps: partial product generations (PPGs) and partial product accumulations (PPAs). Although most operands in decimal multipliers are represented in popular 8421 BCD codes, alternative 4221 and 5211 BCD codes are also sometimes employed, alone or mixed with 8421 codes, to represent the partial products, with a hope that by doing so, the multipliers´ area/time efficiency will be improved. However, study shows that multipliers based on unsuitable mixing of codes, like 4221-8421, can have worse area and timing performance than 8421 multipliers due to the long carry propagation delay of 4221 PPA and the extra 4221-8421 conversions as required. Consequently, in this paper, we propose an 8421-5421 BCD multiplier that is equipped with a simplified PPG based on 8421-5421 recoding and an improved 8421 carry-lookahead adder tree for PPA, and compare it against the two best known multiplier designs using 90nm TSMC technology. The synthesis results have confirmed that the proposed 8421-5421 multiplier achieves the lowest delay and is the most time-area efficient design.