DocumentCode
649499
Title
Electro-thermal co-design of chip-package-board systems
Author
Sohrmann, Christoph ; Heinig, A. ; Dittrich, M. ; Jancke, Roland ; Schneider, P.
Author_Institution
Fraunhofer IIS/EAS, Dresden, Germany
fYear
2013
fDate
25-27 Sept. 2013
Firstpage
361
Lastpage
367
Abstract
We propose an innovative thermal modeling approach that takes into account different “levels-of-knowledge” as they become available during the design phases of microelectronic systems. There are many tools available for thermal simulations which are well-suited for high-precision modeling. However, their applicability severely diminishes if CAD models are not available or modeling time is limited. Especially for electro-thermal co-design, where several spins between modeling and simulation are required, modeling time quickly becomes prohibitively large. By a combination of different techniques our solution offers fast and intuitive modeling, continuous addition of detail, very short simulation times, and open interfaces. In this paper we present our thermal modeling approach based on constructive solid geometry (CSG). We discuss advantages and limits of this solution and demonstrate its performance on an example of industrially-relevant complexity.
Keywords
integrated circuit design; integrated circuit modelling; integrated circuit packaging; CAD models; CSG; chip-package-board systems; constructive solid geometry; electro-thermal codesign; for high-precision modeling; innovative thermal modeling approach; microelectronic systems; open interfaces; thermal simulations;
fLanguage
English
Publisher
ieee
Conference_Titel
Thermal Investigations of ICs and Systems (THERMINIC), 2013 19th International Workshop on
Conference_Location
Berlin
Print_ISBN
978-1-4799-2271-0
Type
conf
DOI
10.1109/THERMINIC.2013.6675192
Filename
6675192
Link To Document