Non-linear thermal simulations of semiconductor devices on system level

A simulation approach on system level is presented. The miniaturization of semiconductor devices causes higher power dissipation density on chip in comparison to predecessors. Therefore fast simulation techniques are required to identify thermal risks in the circuits and to make thermal optimization already in the design phase prior to mass production. The FEM simulators provide accurate results at the expense of long simulation time. However, in the concept or design phase a fast estimation of temperature is needed and an accuracy of 5-15% is usually acceptable. The FEM simulators are not integrated part of IC design tools and require additional skills of designers. To facilitate the work of designers a simulation approach on system level is introduced. The basis is a thermal library implemented in the Cadence environment. The particular parts of the thermal system like die, die attach, metal-oxide-layer, power metallization, lead-frame etc. are implemented as VHDL-AMS instances in this library. Every instance consists of one dimensional T topology RC network rather than non-physical Foster one. This network represents a truncated pyramid consisting of N exponentially distributed cuboids.