Efficient distributed memory management in a multi-core H.264 decoder on FPGA

Author

Jiajie Zhang ; Yu Zheng ; Yu Zhiyi ; Kexin Zhang ; Zhonghai Lu ; Jantsch, Axel

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China

fYear

2013

fDate

23-24 Oct. 2013

Firstpage

1

Lastpage

4

Abstract

Memory management is a challenging issue of multi-core architecture. With growing core numbers, Distributed Shared Memory (DSM) is becoming a general trend. In this paper, a DSM based multi-core architecture is explored and evaluated via an H.264 decoder application. The memory access and communication over Network-on-Chips is managed by the Data Management Engine (DME). Experimental results realized on an Altera Stratix VI show that 9-node distributed memory system increases performance by 1.5x compared to centralized memory. Moreover, the performance of proposed DSM architecture grows linearly with the number of cores deployed.

Keywords

distributed memory systems; field programmable gate arrays; network-on-chip; video codecs; Altera Stratix VI; DME; DSM; FPGA; data management engine; distributed memory management; distributed shared memory; memory access; multicore H.264 decoder; multicore architecture; network-on-chips; DME; DSM; FPGA; H.264 decoder; Multi-core;

fLanguage

English

Publisher

ieee

Conference_Titel

System on Chip (SoC), 2013 International Symposium on

Conference_Location

Tampere

Type

conf

DOI

10.1109/ISSoC.2013.6675256

Filename

6675256