An FPGA based low power multiplier for FFT in OFDM systems using precomputations

OFDM is considered to be the technology of choice for many wireless and wire-line transmission systems. OFDM is the standard for IEEE802.11, digital audio and video broadcast, and DSL broadband internet access. The generation of orthogonal frequencies in OFDM is done by using Inverse Fourier Transform and implemented as IFFT. IFFT (for transmission) and FFT (for receiving) are considered to be very computationally intensive applications. In this paper we introduce a new multiplier for performing FFT (since both FFT and IFFT require the same computation structure, we will use FFT to refer to both of them). First, we use fixed point FFT instead of floating point. The BER due to noise and multipath is studied as a function of the number of bits chosen to represent data in the system. Then, we introduce an FPGA based multiplier using precomputations to be used in FFT. Our proposed multiplier requires less energy and consumes less resources on the FPGA chip compared to a standard fixed point IP core by Xilinx. The proposed architecture is implemented on FPGA using Xilinx Spartan 6 architecture and compared to the traditional implementation of the FFT (IP multiplier by Xilinx). Our proposed multiplier shows a decrease of 50% energy consumption and uses less FPGA resources than a standard IP multiplier.