High speed symbol timing recovery for wideband satellite transmission

This paper accounts for an informative way to implement high speed symbol timing recovery with a parallel structure to overcome time constraint by computational processing. Recently, as wideband satellite transponders that have more than 200 MHz bandwidth have been launched and it´s followed by successive work on transmission protocol in terms of power/bandwidth efficiency using single carrier transmission. For a single carrier transmission, receiver should be able to support minimum 200MHz symbol rate. To realize this objective, straightforward parallel processing to be considered entails increased amount of computational logic and makes it inapplicable to mass production that is necessary for cost effective receiver. In this literature, the blocks that require much time latency have been scrutinized and applied to appropriate parallel architecture. Furthermore, it validates results by means of performance assessment and FPGA implementation.