DocumentCode
649726
Title
Performance analysis of LDPC Convolutional Codes
Author
Baloch, Zahoor Ahmed ; Hussain, Amir ; Hussain, Nasir
Author_Institution
Balochistan Univ. of Eng. & Technol., Khuzdar, Pakistan
fYear
2013
fDate
14-16 Oct. 2013
Firstpage
585
Lastpage
590
Abstract
Low Density Parity Check Convolutional Codes (LDPC-CCs) have the advantage of simple encoding and decoding. ASIC or FPGA implementation of LDPC-CCs have been shown to have very good complexity-performance trade-off. In this paper, we present a class of LDPC-CC and iterative algorithm to decode these codes. The construction technique of our code is simple and easy, compared to other LDPC-CCs, which reduces hardware complexity. The simulation results show that the performance of our proposed codes is better than the LDPC Block codes with the same decoding complexity per information bit. Our code also outperforms its counterpart LDPC-CCs.
Keywords
application specific integrated circuits; convolutional codes; field programmable gate arrays; iterative decoding; parity check codes; ASIC; FPGA; LDPC convolutional codes; LDPC-CC; construction technique; hardware complexity; iterative algorithm; low density parity check codes; simple decoding; simple encoding; Convolutional Codes; Iterative encoding and decoding; Low Density Parity Check Codes;
fLanguage
English
Publisher
ieee
Conference_Titel
ICT Convergence (ICTC), 2013 International Conference on
Conference_Location
Jeju
Type
conf
DOI
10.1109/ICTC.2013.6675426
Filename
6675426
Link To Document