DocumentCode :
649878
Title :
Low-leakage Full Adder circuit using Current Comparison Based Domino Logic
Author :
Naveen, R. ; Thanushkodi, K.
Author_Institution :
Dept. of ECE, Inf. Inst. of Eng., India
fYear :
2013
fDate :
3-3 July 2013
Firstpage :
41
Lastpage :
45
Abstract :
In this paper, a Full Adder is implemented using a Current Comparison Based Domino Logic which has lower leakage and higher noise immunity without dramatic speed degradation. The technique which is utilized in this paper is based on comparison of mirrored current of the pull-up network with its worst case leakage current. The domino circuit technique which is used here decreases the parasitic capacitance on the dynamic node, yielding a smaller keeper to implement fast Full Adder. Thus, this design can be used to build multipliers so that the power consumption and delay are reduced. The leakage current also decreased by exploiting the footer transistor in diode configuration, which results in increased noise immunity. Simulation results of low leakage high speed full adder shows better results in terms of power dissipation compared to other full adders.
Keywords :
adders; circuit noise; logic design; low-power electronics; current comparison; delay reduction; domino logic; low leakage current full adder circuit; mirrored current; multiplier circuit; noise immunity; power consumption reduction; pull-up network; Current Comparison Based Domino; Domino logic; Full Adder;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Current Trends in Engineering and Technology (ICCTET), 2013 International Conference on
Conference_Location :
Coimbatore
Print_ISBN :
978-1-4799-2583-4
Type :
conf
DOI :
10.1109/ICCTET.2013.6675908
Filename :
6675908
Link To Document :
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