Design of high speed and low power new reconfigurable fir filter for DSP applications

This paper presents an architectural approach to the design of Low power and high speed Reconfigurable finite impulse response (FIR) filter. FIR digital filters are used in DSP by the virtue of its, linear phase, fewer finite precision error, stability and efficient implementation. In the proposed architecture, we are introduced pipeline Technique to obtain the high speed. So the proposed architectures offer Low power and high speed compared to the best existing reconfigurable FIR filter implementations in the literature and the proposed architectures have been implemented and tested on Spartan-3 xc3s200-5pq208 field-programmable gate array (FPGA) and synthesized.