Design and analysis of nonlinear AES S-box and mix-column transformation with the pipelined architecture

Cryptography plays an important role in the security of data. It enables us to store sensitive information or transmit it across insecure networks so that unauthorized persons cannot read it[1]. In this paper, we use FPGA chips to realize high data throughput AES pipelined architecture is proposed by partitioning the ten rounds into sub-blocks of repeated AES modules. In this paper we have detailed the alternative design of both direct, inverse Mix Column transforms and high secure nonlinear S-box required in the AES hardware implementation and apply the pipeline architecture for high speed application.