Low power and area efficient reconfigurable FIR filter implementation in FPGA

This paper presents an architectural approach to the design of low power and area efficient Reconfigurable finite impulse response (FIR) filter. FIR digital filters are used in DSP by the virtue of its, linear phase, fewer finite precision error, stability and efficient implementation. The proposed architectures provide the low power and area up to date through changing some other adder in appropriate points making the power and area decrease, And compared to the best existing reconfigurable FIR filter implementations in the literature and the proposed architectures have been implemented and tested on Spartan-3 xc3s200-5pq208 field-programmable gate array (FPGA) and synthesized.