High throughput pipelined implementation of reconfigurable FIR filter for SDR

This paper presents an architectural approach to the design of high throughput reconfigurable finite impulse response (FIR) filter. FIR digital filters are used in [1]DSP by the virtue of its, linear phase, fewer finite precision error, stability and efficient implementation. The proposed architectures provide the highest throughput up to date through inserting some registers in appropriate points making the delay shortest, when implementing the byte transformation in one clock period And compared to the best existing reconfigurable FIR filter implementations in the literature and the proposed architectures have been implemented and tested on Spartan-3 xc3s200-5pq208 field-programmable gate array (FPGA) and synthesized.