Title :
Follower voltage flipped with FGMOS transistors for low-voltage and low-power applications
Author :
de la Cruz-Alejo, Jesus
Author_Institution :
Tecnol. de Estudios Super. de Ecatepec (TESE), Ecatepec, Mexico
fDate :
Sept. 30 2013-Oct. 4 2013
Abstract :
In this paper a new follower voltage flipped (FVF), with floating gate CMOS transistors (FGMOS) is proposed. To demonstrate that the proposed structure with FGMOS transistors is a very suitable structure to solve problems for analog cells design with low voltage and low power, theoretical steps design are presented together with its simulation. The output of the FVF is insensitive to the device parameters and is loaded with a resistive load. The design consists of three FGMOS transistors and one current mirror. Simulated results are compared with those obtained by theoretical analysis. The results show that the proposed FVF in a 0.13μm CMOS process exhibits significant benefits in terms of linearity, insensibility to device parameters, bandwidth and output impedance. The power supply is 0.8V and a power consumption of 81μW, a THD of 3% with a 0.5Vp-p 1GHz sinewave input and a 30KHz load resistance.
Keywords :
MOSFET; current mirrors; integrated circuit design; low-power electronics; CMOS process; FGMOS transistors; analog cells design; current mirror; device parameters; floating gate CMOS transistors; follower voltage flipped; load resistance; low-power applications; low-voltage applications; power 81 muW; resistive load; size 0.13 mum; voltage 0.8 V; Bandwidth; CMOS; floating gate; follower voltage flipped; impedance; low power; low voltage; mirror;
Conference_Titel :
Electrical Engineering, Computing Science and Automatic Control (CCE), 2013 10th International Conference on
Conference_Location :
Mexico City
Print_ISBN :
978-1-4799-1460-9
DOI :
10.1109/ICEEE.2013.6676016