Design of a highly linear fully integrated wideband LNA in 0.13µm CMOS technology

Author

Zafar, Faiza

Author_Institution

Dept. of Electron. Eng., NED Univ. of Eng. & Technol., Karachi, Pakistan

fYear

2013

fDate

Sept. 30 2013-Oct. 4 2013

Firstpage

453

Lastpage

457

Abstract

This work presents the design of a 2.1-3.1GHz wideband Low Noise Amplifier (LNA) in 0.13μm CMOS technology from IBM. A single ended cascode configuration with inductive degeneration is used. The circuit is designed in Cadence and employs feed forward distortion cancellation technique to improve linearity. The layout is designed in Virtuoso XL and post layout simulations are performed using Assura 1.8.0.1 DM. At 2.45GHz, the low noise amplifier has a gain of about 10.0dB, noise figure of 1.66dB, input referred P1dB of -4.78dBm, output referred P1dB of 5.22dBm, IIP3 of +11.1dBm and OIP3 of +21.77dBm consuming 8.48mA from 1.5V supply. This design has the best input referred P1dB and IIP3 reported till date in 0.13μm technology for the desired frequency of operation.

Keywords

CMOS analogue integrated circuits; MMIC amplifiers; UHF amplifiers; field effect MMIC; integrated circuit layout; low noise amplifiers; CMOS technology; Virtuoso XL; frequency 2.1 GHz to 3.1 GHz; fully integrated wideband LNA; highly linear LNA; inductive degeneration; post layout simulation; single ended cascode configuration; size 0.13 mum; wideband low noise amplifier; Complementary metal oxide semiconductor (CMOS); feed forward distortion cancellation (FDC); impedance matching; low noise amplifier (LNA); wideband LNA;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Engineering, Computing Science and Automatic Control (CCE), 2013 10th International Conference on

Conference_Location

Mexico City

Print_ISBN

978-1-4799-1460-9

Type

conf

DOI

10.1109/ICEEE.2013.6676081

Filename

6676081