Substrate effect on UTBB SOI nMOSFET

This paper presents an analysis of the substrate influence on Ultra Thin Body and Box (UTBB) SOI nMOSFETs with and without Ground Plane (GP) implantation comparing experimental results, simulations and a simple analytical model. A good agreement is observed between experimental and simulation results at all back gate bias (V_GB) conditions. However, the simple analytical model for the potential drop at the SOI substrate is only valid for the back interface depleted condition and when it reaches inversion (or accumulation) the model did not fit the experimental results anymore. The simple model can be used within the validity range to study UTBB SOI MOSFET like scalability of front and back oxide thickness for example.