Author_Institution :
Frontier Res. Center, Tokyo Inst. of Technol., Yokohama, Japan
Abstract :
Although silicon-based CMOS devices have dominated the integrated circuit applications over the past few decades, it is expected that the development of CMOS would reach its limits after the next decade because of the difficulties in downsizing and also some fundamental limits of MOSFETs. However, there are no promising candidates which can replace CMOS with better performance and high-density integration for the moment. Thus, we have to stick to the CMOS devices until its end. In order to pursue the downsizing of CMOS for another decade, the development of new technologies is becoming extremely important. Not all the companies can necessarily develop the most advanced technology timely and the competition between the leading semiconductor manufacturing companies becomes very severe for their survive. The current status of the frontend of the technology is as follows: New device structures (FinFET, Tri-gate, and Si-nanowire MOSFETs) are replacing conventional planar MOSFETs. Continuous innovation of High-k/metal gate technologies has enabled EOT scaling down to 0.9 nm in production, however, new materials are necessary for further EOT scaling. Recent advances in new channel material such as III-V/Ge shows promising device performances, however, it is still behind of the state of the art Si-CMOS technologies. comparable to state of the art Si-based MOSFETs. Device demonstration on emerging technologies (such as Tunnel FET, Junctionless FET, Carbon-based FET, ...) is increasing, But we cannot draw a successful story to replace the Si-CMOS and much longer time is needed for implementation of these technologies in future generation devices.
Keywords :
CMOS integrated circuits; III-V semiconductors; MOSFET; elemental semiconductors; germanium; high-k dielectric thin films; nanowires; silicon; tunnel transistors; CMOS devices; FinFET; Ge; III-V-Ge; Si; Si-CMOS technology; Si-nanowire MOSFET; carbon-based FET; channel material; high-k-metal gate technology; junctionless FET; nanoCMOS technology; planar MOSFET; semiconductor manufacturing; tri-gate; tunnel FET; CMOS; FinFET; MOSFET; downsizing; high-k;