A 10Gbps in-line Network Security Processor with a 32-bit embedded CPU

Author

Jie Bai ; Liji Wu ; Niu Yun ; Yang Liu ; Xiangmin Zhang

Author_Institution

Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China

fYear

2013

fDate

16-18 May 2013

Firstpage

616

Lastpage

619

Abstract

This paper presents design and verification of a 10Gbps in-line Network Security Processor (NSP) with a single 32-bit embedded CPU. This NSP is designed to process the IPSec protocol at line speed for the 10Gbps Ethernet. 10Gbps SerDes, IPSec protocol processing module, database query module, and a CPU are designed to be integrated on one chip to form a System on Chip (SOC). The CPU used is OR1200, a 32-bit open source general-purpose CPU with Harvard Microarchitecture. The CPU acts as the controller, bringing flexibility and scalability to the system. Virtex-5 XC5VXS95T FPGA board is used in the verification.

Keywords

embedded systems; field programmable gate arrays; microprocessor chips; system-on-chip; Ethernet; Harvard Microarchitecture; IPSec protocol processing module; OR1200; SOC; SerDes; Virtex-5 XC5VXS95T FPGA board; bit rate 10 Gbit/s; database query module; embedded CPU; in-line network security processor; line speed; open source general-purpose CPU; system on chip; word length 32 bit; 10Gbps; Ethernet; FPGA; IPSec; Network Security Processor; OR1200;

fLanguage

English

Publisher

ieee

Conference_Titel

Wireless and Optical Communication Conference (WOCC), 2013 22nd

Conference_Location

Chongqing

Print_ISBN

978-1-4673-5697-8

Type

conf

DOI

10.1109/WOCC.2013.6676448

Filename

6676448