Implementation of accelerated BCH decoders on GPU

With the development of communication systems, the requirement for efficient error correcting code becomes an important issue. In this paper, we address a parallel software implementation of BCH(Bose-Chaudhuri-Hocquenghen) decoding for HINOC (High Performance Network Over Coax) standard, which is an access network technology aiming at solving the bandwidth limit in user area. A highly efficient parallel decoding algorithm of BCH codes based on CU-DA (Compute Unified Device Architecture) is presented. An iterative decoding algorithm is adopted to implement BCH decoders by virtue of the massively parallel architecture advantage of GPU (Graphic Process Unit). The major concern of the BCH decoders devised on GPU is concentrated on the parallel process capability of the decoding algorithm. Through flexible threads assignment and efficient scheduling strategy, the GPU-based BCH decoders are implemented significantly. Specially, we design and carry out BCH(n=504, k=432, t=7) decoders using the proposed approach. Besides, we evaluate its performance with respect to its CPU-based single-threaded counterpart developed in the C++ language. The experimental results show that our proposed GPU-based BCH decoders achieve a significant speedup of more than 50 times improvement. Furthermore, the implementation of the proposed BCH decoder architecture is scalable to various block lengths and various correctable error numbers, thus providing an efficient and convenient approach to do parallel BCH decoding processes on GPU.