Title :
Design of Reverse Converters for the New RNS Moduli Set
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Author :
Patronik, Piotr ; Piestrak, Stanislaw J.
Author_Institution :
Inst. of Comput. Eng., Control, & Robot., Wroclaw Univ. of Technol., Wrocław, Poland
Abstract :
This paper considers a new balanced residue number system (RNS) composed of four low-cost moduli {2n+1, 2n-1, 2n, 2n-1+1} for odd n. It is complementary to similar already known balanced 4-moduli set {2n+1, 2n-1, 2n, 2n+1+1} ( n odd), because it fills the gap in the sparse 8-bit resolution of dynamic ranges available for this class of 4-moduli RNSs. The first ever design methods of residue-to-binary (reverse) converters for this new RNS are proposed. Three versions of the converter, differing in the composition of calculations and hence resulting in different critical delays and energy consumption, are considered. Synthesis results obtained for the 65 nm technology for the dynamic ranges from 11 to 83 bits suggest that delay, power consumption, and area of the new converters are significantly improved w.r.t. the state-of-the-art converters for the above mentioned 4-moduli set and are comparable to those offered by the converters for two other balanced 4-moduli sets {2n+1, 2n-1, 2n, 2n±1-1} ( n even).
Keywords :
application specific integrated circuits; convertors; delays; residue number systems; 4-moduli sets; Chinese remainder theorem; RNS moduli set; critical delays; energy consumption; residue number system; residue-to-binary converters; reverse converters; size 65 nm; Adders; Algorithm design and analysis; Design methodology; Digital signal processing; Dynamic range; Hardware; Vectors; Application-specific integrated circuit (ASIC); Chinese remainder theorem (CRT); computer arithmetic; digital signal processing (DSP); residue arithmetic; residue number system (RNS); residue-to-binary converter; reverse converter;
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2014.2337237