Automatic Loop-Based Pipeline Optimization on Reconfigurable Platform

Pipelining is an effective technique to improve the performance of a loop by overlapping the execution of several iterations. We consider the pipeline scheduling of loops on reconfigurable platform in this paper. A loop is abstracted as a weighted data flow graph (WDFG), where nodes represent tasks while edges stand for inter-task dependencies. The weights of nodes and edges indicate task execution times and communication overheads respectively. Based on the abstraction, we design a novel and flexible technique for scheduling loops running on reconfigurable platforms using loop pipelining. This results in good parallelism for the loops. To evaluate the performance of the proposed technique, we have demonstrated experiments both with software simulation and hardware evaluation on FPGA-based reconfigurable platform. The experimental results show that our approach has satisfactory performance.