Wireless on Networks-on-Chip

Author

Taskin, Baris

Author_Institution

Dept. of Electr. & Comput. Eng., Drexel Univ., Philadelphia, PA, USA

fYear

2013

fDate

2-2 June 2013

Firstpage

1

Lastpage

2

Abstract

On-chip wireless interconnects are being investigated for applicability on network-on-chip systems of contemporary Multiprocessor Systems-on-chip (MPSoCs). Targeting both 2D and 3D semiconductor technologies, wireless interconnects are established with multiple antennas on the same die or couplers on the layers of a 3D IC package. The wireless interconnects are typically considered as a hierarchical layer or a supplementary network utilized in a hybrid implementation with the traditional wire-based interconnects of the common network-on-chip implementations.

Keywords

antennas; integrated circuit interconnections; integrated circuit packaging; microprocessor chips; network-on-chip; 2D semiconductor technologies; 3D IC package; 3D semiconductor technologies; MPSoC; NoC; contemporary multiprocessor systems-on-chip; hierarchical layer; hybrid implementation; multiple antennas; network-on-chip systems; on-chip wireless interconnects; supplementary network; wire-based interconnects; Antennas; Integrated circuit interconnections; Radio frequency; System-on-chip; Three-dimensional displays; Wireless communication; Wireless sensor networks;

fLanguage

English

Publisher

ieee

Conference_Titel

System Level Interconnect Prediction (SLIP), 2013 ACM/IEEE International Workshop on

Conference_Location

Austin, TX

Type

conf

DOI

10.1109/SLIP.2013.6681675

Filename

6681675